An inductor goes missing from the bill of materials and the board still boots, which is the first clue that this is not a standard H7 design. The STM32H725RGV6 is the VFQFPN68 variant, and ST’s own support answer is explicit: in that 8 x 8 mm, 1.0 mm package VDDLDO is not brought out and only the SMPS configuration is allowed. To restore encrypted STM32H725RGV6 program, start with the supply: a probe on the wrong rail produces a readout that fails checksum for reasons that look like protection but are really power integrity.
Identifying The Supply Pins
| Pin | Role |
|---|---|
| VLXSMPS | Switch node of the internal buck converter |
| VFBSMPS | Feedback input for the SMPS |
| VDDSMPS | SMPS supply input |
| VCAP | Core rail decoupling, 100 nF at each pin |
AN5419 and the RM0468 power-supply tables describe the permitted configurations. With no LDO on this package, VCORE comes from the SMPS and the external inductor and capacitors are not optional decorations. A board that omits them, or routes the feedback trace beside a switching node, will show ripple on the core rail that changes from one read to the next.
Reading Under A Noisy Core
The 550 MHz Cortex-M7, 1 MB of ECC flash and 564 KB of SRAM are identical to the rest of the H725 line. At that clock the margin between a clean flash sense and a marginal one is small, and a switching regulator contributes directly to it. Before attempting anything invasive, capture the core rail on a scope during a read, confirm the ripple envelope, and repeat the same address range several times. If the failures move between runs, the problem is electrical rather than a protection bit.
This is also why a low-voltage glitch attempt on an SMPS-only part is harder to reproduce than on an LDO part. The regulator actively corrects the disturbance, and the correction loop has its own timing. Anyone promising a repeatable fault injection without characterising that loop is guessing. Our notes on defeating readout protection separate electrical preconditions from logical ones.
The Actual Protection Map
RDP uses 0xAA for level 0, 0xCC for level 2, and any other value for level 1, programmed through FLASH_OPTSR_PRG with a reload and reset. STM32H7 blocks RAM access over JTAG even at level 1, so staging a reader in the 564 KB of SRAM is not a shortcut. Level 2 disables SWD and the system bootloader permanently; there is no way back.
PCROP is configured separately through FLASH_PRAR_PRG, aligned to 256 bytes, and turns its region into execute-only memory. Instruction fetches succeed, while data reads, DMA and debug reads fail. H725 order codes are not on the OTFDEC applicable-products list, so the two Octo-SPI interfaces on this die carry plaintext in memory-mapped mode rather than an AES-128-CTR stream. That distinction matters when the board has an external serial flash: on this part, desoldering it yields usable code.
Counting The 68 Pins
A VFQFPN68 has a narrow I/O budget, and the SMPS pin cluster consumes several of it. VLXSMPS, VFBSMPS, VDDSMPS, VCAP, VDD, VSS, VBAT, BOOT0 and NRST together leave far fewer usable GPIOs than the 114 available on the 144-pin members of the same line. That constrains how much of the dual Octo-SPI and FMC interface can actually be wired, so a board built on this package rarely exposes both external memory ports at full width.
What The External Bus Looks Like Here
AN5281 lists the parts with an on-the-fly decryption engine, and H725 order codes are not on it. External Octo-SPI content in memory-mapped mode is therefore plaintext rather than an AES-128-CTR stream. If the board carries a serial flash, reading that device in a programmer yields usable code, and the internal 1 MB array still needs its own separate dump. The boot configuration and any RDP state remain in the MCU, so the two reads are complementary rather than alternatives.
Deliverables And Next Checks
Provide the 1 MB image, the option byte state, the sector write-protection bitmap, and a short record of the supply conditions under which the read was taken. Verify the vector table and compare two independent reads. The STM32F405VG program recovery case shows the same verification discipline on an older Cortex-M4, and the encrypted STM32F302RD cloning example covers a part where the external memory is genuinely protected.
If the board cannot be powered cleanly in-circuit, the chip-level readout service can work with the device removed from the SMPS network. For a comparison with the 100-ball version of the same line, see the STM32H725VGH6 dual-regulator variant.