Same 100 balls, same 0.8 mm pitch, same 1 MB flash: a different power tree. The STM32H725VGH6 sits in the TFBGA100 body that the H723VGH6 also uses, but the 5 in the type number marks the line with an internal SMPS alongside the LDO. To dump protective STM32H725VGH6 heximal reliably, treat the two regulators as part of the evidence, not as a background detail on the schematic.
Supply choice: what the schematic reveals
An H723 in this package is LDO-only. An H725 can scale VCORE through the buck converter while retaining the linear regulator for other configurations, and the board shows which one the designer selected by the inductor and the VCAP network. Mixed supply modes mean the core rail can sit at different voltages during run, stop and a debugger attach, so a read taken at one operating point is not automatically reproducible at another.
That matters for fault injection. A glitch calibrated against an LDO-fed core will behave differently when a switching loop is correcting the same disturbance. Record the regulator configuration before choosing an injection point, and repeat any read at the same clock and voltage scaling. Our protection bypass methodology treats these electrical preconditions as a separate checklist.
Array layout: unchanged from the 550 MHz line
1 MB of embedded flash from 0x08000000, 564 KB of SRAM divided into 128 KB of DTCM, 432 KB of system RAM and 4 KB of backup SRAM, all with ECC. Two Octo-SPI interfaces support XiP, but H725 order codes are absent from the AN5281 OTFDEC product list, so external memory-mapped contents are not wrapped in an AES-128-CTR stream. If the board carries a serial flash, it is worth reading as plaintext rather than assuming a decryption problem.
Regression: the H7 detail that survives an erase
RDP here follows the standard H7 encoding: 0xAA is level 0, 0xCC is level 2, and any other value is level 1. Writes go through FLASH_OPTSR_PRG and need an option-byte reload plus a reset. Dropping from level 1 to level 0 is allowed, but it triggers a full mass erase of user flash.
ST documents a second effect that is easy to overlook: after that regression the PCROP configuration remains active. A team that erases a board expecting every protection bit to clear will find the execute-only pocket still refusing data reads. PCROP regions are programmed through FLASH_PRAR_PRG, aligned to 256 bytes, and limited to one per bank; code inside must be compiled execute-only with no literal pools. On this family the OTP and memory-type comparison is a useful companion when someone assumes an erase resets one-time-programmable areas too.
Pin compatibility: what it really means
The H723VGH6 and the H725VGH6 share a 100-ball footprint and a 1 MB array, which invites a BOM substitution that is not actually drop-in. One is LDO-only, the other expects an SMPS network. Swapping the silicon without changing the inductor, feedback and VCAP components leaves the core rail outside its intended operating point, and a readout taken on such a board may fail for electrical reasons that look exactly like a protection response. Confirm the marking on the package, then confirm the supply components around it. Neither check is a substitute for the other.
The two external windows
Two Octo-SPI interfaces give this part separate memory-mapped windows for code and data, and a product can place a font bank, a waveform table or a secondary application in either of them. Because this order code has no OTFDEC engine, those windows carry plaintext. A delivery scoped only to the internal 1 MB will miss that material entirely. Ask which devices are fitted, record their part numbers, and include their raw contents alongside the on-chip image so the customer can rebuild the full memory map rather than guessing at a hole.
Verification: what a finished image contains
Capture the full 1 MB, the option byte snapshot, the sector write-protection bitmap and the OTP area. Read twice at a fixed supply configuration and compare. Flash ECC turns marginal cells into explicit failures, so moving failures between runs point back to the regulator rather than to the array. Confirm that the reset vector and stack pointer land inside the recovered range, and note whether any PCROP region was declared by the customer.
The STM32F407IG source code dump walks through the same evidence chain on a larger M4 package. Where the 100-ball body leaves no accessible SWD test points, the device-level readout service covers package and die access. For the SMPS-only 68-pin sibling, see STM32H725RGV6 program restoration.