Two order codes, one die. The STM32H723ZGT6 and the 100-ball VGH6 share the same 550 MHz Cortex-M7 core, the same 564 KB of ECC-protected SRAM and the same 1 MB flash array; what changes is the 20 x 20 mm LQFP144 body and the 114 I/Os it exposes. Anyone trying to recover protected STM32H723ZGT6 binary should begin by reading the package marking, because the letter T in the fourth position is a package code, not a temperature or a security grade.
| Code | Package | Flash | I/O | Supply |
|---|---|---|---|---|
| ZGT6 | LQFP144 20 x 20 mm | 1 MB | 114 | LDO |
| VGH6 | TFBGA100 8 x 8 mm | 1 MB | 80 | LDO |
| ZEI6 | UFBGA144 7 x 7 mm | 512 KB | 114 | LDO |
1. Read The Option Bytes Before Touching The Array
RDP lives in an 8-bit option byte field accessed through FLASH_OPTSR_CUR and FLASH_OPTSR_PRG. The values are 0xAA for level 0, 0xCC for level 2, and anything else for level 1. Programming a new value is not instantaneous: an option-byte reload and a subsequent reset are required, so the value visible to a debugger immediately after a write can be stale. Record both the current and programmed registers before deciding which route is viable.
At level 1 the debug port still exists, but flash, backup SRAM and backup registers are unreadable from outside. Level 2 removes the port and the system bootloader permanently. A mass erase is the price of returning from level 1 to level 0, and that erase covers the entire user flash, not just the sectors you intended to inspect.
2. Map The Sectors, Then The Interfaces
The 1 MB array is organised in 128 KB sectors, and write protection is controlled per sector through the FLASH_WPSN registers. That granularity matters when a customer asks for a partial image: a single protected sector can be the difference between a complete firmware and a file with an unexplained hole in the middle.
Two Octo-SPI interfaces and a 16-bit FMC are available on this 144-pin part. Neither interface changes where the primary application lives, but both can hold a secondary bootloader, a lookup table or an FPGA bitstream that a customer considers part of the deliverable. Ask which external devices are fitted before scoping the job. A general discussion of how program memory types differ helps separate on-chip flash from external serial storage, and the STM32F103RB recovery notes cover a much smaller array with the same RDP logic.
3. Handle PCROP As A Separate Question
PCROP converts a flash region into execute-only memory. Instruction fetches succeed; data reads, DMA and debug access do not. Regions are set with FLASH_PRAR_PRG, aligned to 256 bytes, and limited to one per bank on this architecture. Firmware intended for such a region must be built with an execute-only compiler switch and must not place constants or branch tables inside it.
Because PCROP is configured independently of RDP, a part can be fully readable at level 0 and still hide a library in an execute-only pocket. On STM32H7 the configuration also survives a level 1 to level 0 regression, so the mass erase that clears the array does not automatically clear the protection map.
3b. Boot Straps On An Exposed Package
BOOT0 and the boot address option bytes decide whether the device starts from user flash, system memory or an Octo-SPI mapped window. On an LQFP144 every relevant signal reaches a package edge, so a board-level attach is far easier than on the TFBGA100 sibling, but the straps are equally visible and easy to disturb. Record their state before asserting NRST: a part entering the system bootloader may never expose the user array to the debugger, and one configured to boot from external memory will execute code that a later attach cannot see.
4. Verify Against The Board, Not The Datasheet
Recover a full image, then confirm the reset vector and stack pointer fall inside it, check the sector write-protection bits against the recovered configuration, and compare a second read for bit-for-bit equality. ECC on both flash and SRAM tends to surface marginal cells as outright failures, which is preferable to a quietly corrupted byte. Our readout methodology page sets out that verification sequence in more detail.
If the debug header is unpopulated or the part is already at level 2, the contact route for device-level work is the practical next step. The STM32H730IBK6Q value-line analysis is also worth reading when the board carries an external serial flash that turns out to hold most of the application.