The letter E is the whole problem. In ST ordering codes the fourth character is a flash density code, and E means 512 KB. A BOM that lists the STM32H723ZEI6 alongside a 1 MB binary is describing two different things, so the first step in any attempt to readout secured STM32H723ZEI6 code is to decode the part number rather than trust the firmware size quoted in a ticket.
Density Codes And Address Ceilings
| Density code | Flash | Upper address | Typical order code |
|---|---|---|---|
| E | 512 KB | 0x0807FFFF | STM32H723ZEI6 |
| G | 1 MB | 0x080FFFFF | STM32H723ZGT6 |
| I | 2 MB | 0x081FFFFF | STM32H745BIT6 |
The core is unchanged: a Cortex-M7 at 550 MHz with a double-precision FPU, 32 KB instruction and 32 KB data caches, and 564 KB of SRAM. What changes is the array behind 0x08000000. The ZEI6 comes in a UFBGA144 body, 7 x 7 mm at 0.5 mm ball pitch, with 114 I/Os. Ball-grid packaging means the SWD pads are under the die, so a board-level readout depends on whether the designer broke those signals out to test points.
Why Overreading Wastes Time
A readout script written for the 1 MB sibling will happily request 0x08100000 and beyond. On the 512 KB part those addresses are not user flash; they either return a bus error or a constant pattern that looks like plausible data until someone tries to disassemble it. Sector count, write-protection bitmaps, and any PCROP boundaries all scale with the actual density, so they must be recomputed rather than copied from a 1 MB project.
A full-chip erase is similarly bounded. It clears the 512 KB array, the option bytes that the regression is allowed to change, and any volatile configuration that depends on them. It does not extend into the two Octo-SPI memory windows, and it does not reach an external serial flash that may hold a graphics asset bank. The OTP versus flash comparison explains why a one-time-programmable area of 1 KB behaves differently from both.
Protection Layers On This Die
RDP remains the primary gate. 0xAA is level 0, 0xCC is level 2, and any other value is level 1, written through FLASH_OPTSR_PRG and activated by a reload plus reset. STM32H7 closes RAM to JTAG even at level 1, which rules out the classic approach of loading a small reader into SRAM and dumping flash from inside the chip. Level 2 is irreversible and disables the debug port together with the system-memory bootloader.
PCROP adds an execute-only region on top of that. It is programmed through FLASH_PRAR_PRG, aligned to 256 bytes, and limited to one region per bank. Fetch as instructions works; reads as data, DMA access and debugger access all fail. On this family ST also documents that PCROP survives the level 1 to level 0 regression that mass-erases the array. That detail is easy to miss and expensive to discover after the erase has already happened.
Ball Grid Access And The One-Time Area
The ZEI6 uses a UFBGA144 at 0.5 mm pitch, so SWD, JTAG-DP and NRST terminate under the die. Whether the job stays at board level is decided by the PCB: a four-layer board with test points on the back is workable, a two-layer board with no breakout is not.
A separate 1 KB one-time-programmable area and a 96-bit unique ID sit outside the main array. They are not flash and do not behave like flash: an erase leaves them intact, and customers frequently use them for calibration constants, a serial number or a licence binding. At RDP level 2 OTP is no longer readable from outside either, which is worth stating in the quote before anyone assumes the small areas are always recoverable. These small areas also survive the level 1 to level 0 regression that mass-erases the main array, so they must be captured separately rather than reconstructed from an erased device.
Evidence To Hand Over
Deliver the 512 KB image with its vector table, the option byte snapshot, and a note recording which sectors reported write protection. Read twice and compare; flash ECC on this line makes marginal cells fail loudly instead of flipping silently. Compare the recovered reset vector against the schematic boot configuration, and check whether the customer expects the external Octo-SPI contents as part of the same package. The NVRAM extraction notes cover the separate problem of battery-backed configuration data, and the ARM7 STM32F107 case shows a readout where the boot configuration decided everything.
Where the ball grid leaves no usable test points, our device-level service handles package and die access. For a cross-check on the same silicon in a different body, see the STM32H723VGH6 package analysis.