Start at the last address and work backwards. On a 2 MB STM32H7 the upper half of the image can silently come from the wrong bank, because the STM32H745BIT6 implements dual-bank flash with a bank-swap option byte. Reverse engineering locked STM32H745BIT6 chip therefore begins with the memory map, not with the debugger. The I in BIT6 is the density code for 2 MB, and the B is the 208-pin LQFP, 28 x 28 mm, with 148 I/Os.
Two banks, two address windows
| Bank | Default range | Sectors |
|---|---|---|
| Bank 1 | 0x08000000 – 0x080FFFFF | 8 x 128 KB |
| Bank 2 | 0x08100000 – 0x081FFFFF | 8 x 128 KB |
SWAP_BANK_OPT can exchange the user sector mapping after a boot load. A readout taken with the bit set and a linker script written for the default order will produce an image whose vectors are in the wrong place, and the failure looks like corruption rather than configuration. Record the bit, then read both windows and keep them in their observed order. Write protection is applied per 128 KB sector through the FLASH_WPSN registers, so the protection bitmap has sixteen entries and should be captured with the image.
The dual-core complication
This is a Cortex-M7 at 480 MHz plus a Cortex-M4 at 240 MHz, with 1 MB of RAM split into 192 KB of TCM, 864 KB of user SRAM and 4 KB in the backup domain. One debug port exposes two AHB-APs, one per core, and the selected AP determines which address view and which clocked peripherals are visible. D1, D2 and D3 can be gated separately; a session attached while the M4 domain sleeps is not looking at the same device as one attached at full run. Note the core, the AP and the domain state alongside every dump.
Protection that applies to the whole die
RDP is a single option byte field shared by both cores. 0xAA is level 0, 0xCC is level 2, and any other value is level 1; writes go through FLASH_OPTSR_PRG and require an option-byte reload plus a reset. Level 1 closes flash, backup SRAM and backup registers to external reads, and STM32H7 additionally keeps RAM closed to JTAG after a system reset. Level 2 is permanent, disabling SWD, JTAG and the system-memory bootloader with no regression path.
PCROP marks a region execute-only through FLASH_PRAR_PRG, aligned to 256 bytes, with one region per bank. Data reads, DMA transfers and debug reads all fail there, while instruction fetches succeed. On this family ST documents that the PCROP configuration survives a level 1 to level 0 regression even though that regression mass-erases the array. Active tamper detection is also part of the security list. This order code is not in the AN5281 OTFDEC applicable-products table, so its Quad-SPI window carries plaintext in memory-mapped mode.
208 pins change the board, not the core
The LQFP208 body exposes 148 I/Os, enough to wire a 32-bit FMC bus to SDRAM, NOR or PSRAM without multiplexing everything through a narrow port. A product can therefore keep a substantial part of its code or data off-chip, and a readout scoped to the internal 2 MB will miss it. Check the fitted external memory and record its part number alongside the internal image. The same dual-core and RDP rules apply to the die; what changes is how much of the system sits outside it.
Where the road ends
At RDP level 2 there is no software path back. SWD and JTAG are permanently disabled, the system-memory bootloader is gone, and the option byte cannot be regressed. A proposal that promises to unlock such a part by rewriting configuration bytes is describing a different device. Say so early, document the observed level, and limit the deliverable to what can be established from the board and the package.
Rebuilding A Defensible Image
Assemble both banks in observed order, attach the SWAP_BANK_OPT state, the sixteen-sector write-protection bitmap and the option byte snapshot. Read twice at a fixed supply and clock, and compare; flash ECC makes marginal cells fail explicitly rather than corrupt quietly. Confirm that the reset vector and stack pointer fall inside the recovered 2 MB, and check whether the customer expects the Quad-SPI contents as part of the same delivery. The NVRAM extraction notes cover the separate case of battery-backed configuration, and the STM32F405VG program recovery shows the same verification discipline on a much smaller array.
For the 1 MB, 176-pin member of this family, see STM32H745IGT6 data reading. The LPC2468 EMC analysis is a useful comparison for another part where an external bus changes the memory map. Where the debug port is already closed, the contact route for chip-level work is the remaining option.