The J-Series Way Of Being Different
The PIC18F24J10 introduces everything that makes the J-line distinct: a 2.0-3.6 V supply (the F variants run the core from an on-chip regulator tapped at the VDDCORE/VCAP pin), no data EEPROM, a 40 MHz clock ceiling with no fast internal oscillator, and flash endurance of 1,000 cycles with emulated-data routines instead of a true EEPROM. In a 28-pin package it carries 16 KB of program memory (0x0000-0x3FFF in byte terms, 8,192 instructions), 1,024 bytes of SRAM, ten channels of ten-bit ADC, two comparators, an MSSP, an enhanced USART and one CCP module.
Lock Model On PIC18
Configuration moves to the 0x300000 window on PIC18: CP0/CP1 code-protect bits, WRT write-protect bits, and the boot-block controls. Erased configuration bytes read 0xFF; protected arrays return 0x0000 on sixteen-bit instruction fetches. The device ID at 0x3FFFFE and revision at 0x3FFFFF stay readable, which anchors identification. Recovery sweeps the array through the programming specification exactly as production programming did – the lock changes what reads return, not what the programmer can do.
Sweep Rules
– Array: 0x0000-0x3FFF (16 KB byte-addressed). – Configuration: 0x300000 window. – ID: 0x3FFFFE-0x3FFFFF.
Boundary discipline matters against the 32 KB PIC18F25J10 in the same package. The VCAP capacitor on the regulator pin is the first hardware suspect when an on-board interface stays silent – aged MLCCs fail before protection logic ever engages.
Image Anatomy
PIC18 images are byte-oriented with sixteen-bit instructions packed in pairs; the disassembly reads linearly once the even/odd split is handled. A 24J10 image shows the enhanced USART setup, the MSSP init, and a compact application around 1 KB of SRAM. Emulated-EEPROM routines – if present – cluster near the top of the array and hold the persistent parameters.
The Session And Deliverables
Identify, read the configuration window, sweep the array, verify. Nothing is erased; the part returns to service. Deliverables: HEX file, annotated disassembly, configuration report for byte-identical re-flashing, checksum tied to the die. For the 32 KB sibling, see the PIC18F25J10 page; the 40/44-pin members are covered on the PIC18F44J10 page.
Sixteen Kilobytes On The First J Generation
The PIC18F24J10 carries 16 KB at 0x0000-0x3FFF, 1,024 bytes of SRAM, ten ten-bit ADC channels in the 28-pin body, two comparators, and the standard PIC18 peripheral set with no remappable pin layer and no data EEPROM. It runs to 40 MHz at 2.0-3.6 V and predates the J11 generation, which is why its images read differently: pin functions are fixed by the datasheet rather than assigned through a table.
Fixed Functions Make A Readable Dump
Because there is no PPS, a peripheral enable implies its pins. A UART block therefore names the transmit pin, an ADC channel selection names the input, and the recovered image carries its own wiring description without any table to decode. On boards where the schematic has been lost this is a real advantage, and it is the reason J10 jobs often need less back-and-forth than J11 jobs of the same size.
– Array: 0x0000-0x3FFF, 0x3FFF erased, 0x0000 protected. – Configuration: 0x300000-0x300007. – ID: 0x3FFFFE-0x3FFFFF.
Supply Rails And The VCAP Trap
The J10 family routes the core supply out to VDDCORE and requires a capacitor on VCAP. When that capacitor is open the part fails to enter programming mode and looks dead, which is the single most common false alarm on this die. Moving the device to a bench socket with a known-good capacitor resolves the question in under a minute and saves shipping a healthy part back and forth.
Deliverables
HEX at word addresses, annotated disassembly with the fixed-pin peripherals named, configuration report, checksum tied to the die. Protection as found, part returned serviceable.
To copy a locked 24J10, use the services desk or the contact form.