Hundred pins is the threshold where the Ethernet options on this family open up. The 64-pin F437 is effectively an RMII-only design; the VGT7 has enough pads to route a full MII interface and still bring out the two QSPI ports, the external memory bus and enough UARTs to look like an industrial gateway. That difference in routing is the first thing to understand about a board that arrives with this marking.
Sixteen Pins Versus Seven
| Interface | Signals | Practical fit |
|---|---|---|
| MII | TXD0-3, TXEN, TXCLK, RXD0-3, RXDV, RXCLK, RXERR, COL, CRS, MDC, MDIO | 100-pin and above |
| RMII | TXD0-1, TXEN, RXD0-1, CRSDV, REFCLK, MDC, MDIO | 64-pin and above |
The seven-signal version halves the pin cost and runs both directions from a single 50 MHz reference. The sixteen-signal version keeps separate transmit and receive clocks, which is what a design needs when the PHY runs at 10 Mbit and the two directions genuinely differ.
For a recovery the difference is observational: an RMII bus carries everything on two data lines in each direction and is easy to overlook, while MII spreads traffic across eight lines that are hard to mistake for anything else.
Why The Package Decides It
The controller is the same block in both packages. What changes is whether the pads exist. On the 100-pin part the designer also has to choose between MII and the external memory interface for some pins, and the choice is frozen in the firmware’s pin configuration — which is one of the first things we read out of the startup code.
The Array Behind It
None of the network routing changes the memory system. One megabyte of flash in two banks, 4 KB sectors, the second bank behind its own register pair, 384 KB of SRAM configurable to 512, three 12-bit converters at 5.33 Msps, two DACs, thirteen general-purpose 16-bit timers of which three are motor-oriented, two CAN controllers, two USB full-speed controllers, two SDIO ports.
The protection set is the family standard: whole-array access protection, per-sector erase and program protection, sLib with a password-protected range that executes but reads as 0xFF, and no irreversible advanced protection mode. A megabyte part can carry a large library, and boundaries fall on 4 KB multiples.
Sector, sLib And The 512K Line
Two boundaries matter and they are unrelated. The 512 KB line is a register boundary — above it the controller is driven through a second set of registers — and the sector boundary is the unit of protection. Confusing them produces the classic bad dump in which the upper half reads as zeros because it was addressed through the lower bank’s registers.
On the library side, the same rules as everywhere: no first sector, nothing below four kilobytes, password required to clear, and clearing erases the whole array.
Bench Notes: Clocks And The PHY
A networked board arrives powered, with a PHY on the other side of the RMII or MII bus holding lines during reset. Two failures follow. The first is a part that will not enter a loader because the PHY drives a boot pin. The second is a brown-out during the read, because the PHY and its magnetics draw current the supply was never sized for.
We isolate the PHY where the layout allows, or power the board from a supply that can absorb the transient. The reference clock is worth checking too: with RMII everything derives from one 50 MHz source, and a marginal oscillator makes the interface fail in ways that look like firmware bugs.
What We Return
Two bank images and a merged binary, the configuration byte governing the SRAM split, a sector and library map, and a note on the network interface the firmware configures — MII or RMII, the PHY address it polls, and whether the design expects a second image for updates. That last detail frequently decides whether the recovered code is complete or merely the bootloader.
The 64-pin version with RMII is covered in extracting encrypted AT32F437RGT7 code; the same package without the network block is at copying a protected AT32F435VGT7 flash. Scope and lead times are on the services page, and specific boards can be discussed through contact.