Six DMA channels sound like a spec-sheet number until a recovered image shows you what they were for. The PIC32MX230F064B divides them by design: four general-purpose channels for application streaming, and two more wired exclusively to the USB controller. Firmware that uses the division well — audio, sensor bursts, display feeds on a 64 KB part with a full-speed USB port — organizes its whole memory layout around those channels. The layout survives in the flash; the discipline is knowing how to read it.
The Two Kinds Of Work
General channels move application data: converter results into a ring buffer, parallel-master-port bytes to a display, timer-driven pulses to an output pattern. Their descriptors — source, destination, count, cell size — are written by firmware at startup and live in SRAM, which vanishes at power-off. But the code that writes them survives, and from it the whole transfer topology can be reconstructed: which peripheral fed which buffer, at what rate, under which interrupt. For a product whose value is the data path — a sampler, a logger, a bridge — that topology is the product’s operating manual.
The USB-dedicated channels tell a complementary story. They exist so descriptor transfers and endpoint traffic never contend with application streaming, and their configuration in the image reveals the device’s protocol personality: endpoints claimed, transfer types, buffer arrangements. Paired with the descriptor tables themselves, they let a reader reconstruct what the device says about itself on the bus without plugging anything in. The 210F016C page treats the descriptor layer as its main subject; this is the machinery behind it.
What “EEPROM Content” Means Here
Purchase orders for this part often ask for EEPROM data, and the part has none — like the rest of the MX1/2 generation, it emulates persistent storage in program flash through a software layer that appends records into pages and compacts them when they fill. On a 64 KB array from 0x1D000000 to 0x1D00FFFF the emulated region is usually a small, identifiable district: record headers, sequence numbers, superseded copies of the same setting. A recovery report that maps the district and marks the current records delivers what the purchase order actually wanted. The 210F016B page explains the emulation mechanics in detail.
A closing note on scope: the read itself never changes with density. Whatever the channels carried, the capture covers both partitions with the same two-pass verification, and the interpretation layers on top. Customers who need only the HEX get the same rigor as customers who need the schedule; the difference is what the report adds, not what the read skips.
The Peripherals Behind The Channels
Sixty-four kilobytes of flash on this part funds a specific peripheral story: the parallel master port for external displays or memory-mapped devices, the I2S audio port in all four framing modes, the RTCC calendar, and the CTMU for capacitive touch and precision timing. Each of them is a DMA customer. The display refreshes from a line buffer on one channel; the audio interface streams samples on another; the converter results land in a ring on a third. What the general channels do not serve, the USB-dedicated pair takes for endpoint traffic. The recovered image shows the division as clean register clusters per channel, and the clusters reconstruct into a schedule: what moves, how often, at what priority. A product owner who has never seen that schedule written down learns more about their own device from it than from any specification they hold. Two captures, two comparisons, one schedule — that is the arithmetic of a complete job on this part.
Capture And Protection
The mechanical read covers both partitions: 64 KB of program flash and the 3 KB boot bank from 0x1FC00000 to 0x1FC00BFF, whose last page holds the DEVCFG words — oscillator chain, watchdog, debug channel, and the code-protect bit at DEVCFG0 bit 28, active low. Armed, that bit blocks external reads of both partitions, and Microchip’s specification names the chip erase as the only exit — an exit that destroys the firmware. Write-protect fields guard pages during execution but never block a reader, and confusing the two is the classic misdiagnosis. Reading configuration first is what keeps the promise list honest; the copy protection page frames the assessment.
Verification is two independent captures of each region compared word for word, plus a device ID read to pin the die — the 28-pin footprints of this density range are shared, and the ID is the only reliable density check. Page geometry is 256-word erases, 32-word program rows; erased flash reads all ones and the live-code boundary is mapped. The reading process page details the sequence.
The Report That Earns Its Fee
For a DMA-heavy product, the raw HEX is the least of the deliverable. The useful artifact is the reconstructed transfer topology: channel assignments, buffer maps, interrupt rates, the emulated-EEPROM district, the endpoint structure. That is what lets a product owner maintain, port, or defend the design. The chip extraction analysis service packages exactly that, under the terms on the NDA page. Six channels are easy to count; what they carried is the part that matters.
The full family index, with page geometry and package for every part, sits on the PIC32MX extraction overview.