Most clones are tested on a bench with a power supply and a multimeter. A board that talks to another processor over a parallel bus needs a different test, because the failure mode is not “dead” — it is “the host reads stale data and the machine behaves oddly”.
The PIC18F4523 carries 32 KB of program memory — 16,384 instruction words — with 1,536 bytes of SRAM, 256 bytes of data EEPROM, 36 I/O pins, thirteen channels of 12-bit ADC, one CCP and one ECCP module, and a parallel slave port. It comes in 40-pin PDIP and 44-pin TQFP or QFN, and it shares DS39755 with the 16 KB PIC18F4423.
What the PSP Actually Is
The parallel slave port turns the microcontroller into a peripheral on someone else’s bus. Three control lines — read strobe, write strobe, chip select — plus an 8-bit data bus on PORTD, all driven by an external host. The host writes a byte, the port raises an interrupt, firmware reads it. The host reads a byte, firmware must have put one there.
It exists on the 40/44-pin members only, which is why the feature is easy to forget: it is absent from the 28-pin devices and from most one-page summaries.
One Bit Turns the Ports Around
The port is not enabled by a peripheral register in the usual sense. It is enabled by PSPMODE, which is bit 4 of TRISE — the port direction register. Set it and PORTD becomes the data bus in both directions, with PORTE supplying the control inputs. Clear it and PORTD is an ordinary output port again.
That design decision makes a specific failure possible. Firmware that never sets PSPMODE still compiles, still runs, and still drives whatever it drives on PORTD as a normal output. The host reads the bus and gets whatever the port latch happens to hold, which on a quiet system is often a stable, plausible value. The machine appears to work until the host asks for a byte that should change.
PSPCON carries the status flags — input buffer full, output buffer full, input buffer overflow — and the wait-state control. A host that assumes the original board’s timing will sample before the buffer is full if the wait configuration differs.
Why This Survives a Flash Copy
Here is the uncomfortable part: the port configuration lives in code, written at startup, not in the configuration words. A complete flash read carries it, so a clone built from a complete read gets it right.
The problem is not the copy. It is the *verification*. A rebuild team programs a blank part, powers the board, sees the display light up and the relays click, and signs it off — the host bus was never exercised, because the host is on another board that is not on the bench. The failure appears at system integration, attributed to the firmware rebuild rather than to an untested interface.
What to Test Instead
Three checks that need the host:
| Check | Pass condition |
|---|---|
| Host write, MCU read | The byte appears in the firmware’s buffer and the overflow flag stays clear |
| Host read after MCU write | The value matches the most recent write, not the previous one |
| Back-to-back transfers | No overflow flag set at the host’s real transfer rate |
The Donor Question
The 4523 and the PIC18F4520 look identical on paper: same 32 KB, same package, same peripherals. They are different datasheets — DS39755 versus DS39631 — and the ADC is the visible difference. Ten bits on the 4520, twelve on the 4523.
For a board that uses the parallel port to hand analogue results to a host, that difference is a factor of four in every transferred value, with no error flag and no obvious symptom beyond numbers that are slightly wrong. If a 4520 has been substituted as a donor, the bus test above will pass and the readings will be wrong.
Scope
A 4523 job is a 32 KB read in four protection blocks, twelve configuration bytes at 0x300000, 256 bytes of EEPROM at 0xF00000, and the device and revision IDs. The extra step that makes it usable is the bus: if the board has an external host, say so at the start, because the acceptance test depends on it and the chip extraction analysis note should list the interface as a verification item.
Reading firmware out of a board with a parallel interface is routine, and the read the firmware page covers the sequence. What is specific here is that “it boots” is not a test. Send the board photograph showing both connectors — the host header is the clue that this part was chosen for its port rather than its flash size — and contact us with the marking.