PIC18F2331: Motor Control On Twenty-Eight Pins

The 28-pin member of Microchip’s power-control family packs a fourteen-bit PWM module, a quadrature encoder interface and a 200 ksps converter into a package the size of a large postage stamp. Designs built on it are single-axis drives: a pump, a fan, a small conveyor, a valve actuator with feedback.

Map

Eight kilobytes is four blocks of two, and the boundaries sit at 0x0800, 0x1000 and 0x1800 above the start of the array; a separate bit guards the boot block. On a drive the distribution is predictable: the current loop and the PWM setup land in the first block because they are the code that runs first, the speed loop and ramp tables take the second, and the last two hold fault handling and the parameter defaults.

768 bytes of SRAM is more than the sibling parts offer and still not enough for a position history, which is why encoder designs on this device keep a count and a delta rather than a trace. EEPROM 256 bytes at 0xF00000, configuration words at 0x300000, five converter channels on twenty-eight pins.

The Control Hierarchy

A drive on this part runs two loops: a fast current loop in the PWM interrupt, and a slower speed loop in the timer interrupt. The ratio between them is a design decision that shows in the code as a counter dividing one interrupt rate down to the other.

That ratio matters for a rebuild. A current loop at sixteen kilohertz with a speed loop at one kilohertz is a typical arrangement, and a replacement that runs both at the same rate will either miss current events or waste cycles on speed calculation.

The constants inside the current loop — proportional gain, integral gain, and the limit that clamps the integrator — are in the image as integers, and they were tuned against a specific motor and bridge.

Encoder Handling At 768 Bytes

The quadrature interface provides a hardware position count. Firmware either samples it at a fixed interval and differentiates, or uses the capture channels to measure edge timing. The first is cheap and lags at low speed; the second is precise and consumes interrupts.

With 768 bytes of RAM there is no room for a position history, so designs keep a current count, a previous count and a delta. That structure is easy to recognise and easy to reproduce.

Fault Policy

The power-control module accepts hardware fault inputs that disable the outputs within a few cycles. The firmware adds software protection on top: overcurrent from the converter, stall from the encoder, undervoltage from the supply. Each has a threshold, a debounce count and a response.

On a drive, the response is what matters: immediate latch, retry with delay, or derate and continue. The choice is a handful of branches and a large difference in field behaviour.

EEPROM

256 bytes at 0xF00000, unprotected. Speed limits, acceleration, current limit, encoder counts per revolution. Four values that make a drive specific to a machine, all readable on a locked device.

Current Sense Timing And The Sample Point

On a switching bridge the current signal is only meaningful during part of the PWM period. A shunt on the DC bus produces a ramp that rises while the high side conducts, rings when it turns off, and decays through the freewheel path; sampling at the wrong moment returns either the ringing or nothing at all. Firmware therefore triggers the converter from the PWM module’s special event output with a fixed delay, and that delay is a constant tuned to the gate driver’s propagation time and the amplifier’s settling. It lives in the image as a compare value rather than as a loop, so it is easy to find and easy to get wrong. A rebuilt drive that trips on a current that cannot exist is sampling during the transient; one that reads low by a fixed fraction is sampling after the ramp has already decayed. Both are one number away from correct, and the number is in the dump next to the PWM period.

Access

28-pin SPDIP and SOIC. Locked parts are opened only for owners through the service desk. The copy-protection overview covers the bits, and the analysis workflow covers verification.

The 40-pin member at the same capacity is the PIC18F4331; the 16 KB 40-pin member is the PIC18F4431.