Two devices in the XMEGA range carry an identical 64 KB array, an identical 2 KB of EEPROM and an identical 4 KB of RAM. They are not interchangeable, and the difference is not the memory. It is everything around it.
The Array Is the Same, the Machine Is Not
The ATxmega64A3 is the 64-pin member of the A3 line. The ATxmega64A1 is the 100-pin member of the A1 line. Both hold 64 KB of application flash arranged as 256 pages of 256 bytes, both have a 4 KB boot loader of 16 pages, both carry 2 KB of EEPROM across 64 pages of 32 bytes, and both have 4 KB of SRAM.
What differs is the pin count and everything that follows from it. The A3 exposes 50 general-purpose lines on a 64-lead package; the A1 exposes 78 on a 100-lead package. Those 28 extra pins are not spare: they are the second half of the serial ports, the extra SPI channels, the second DAC and the additional timer channels.
| Feature | ATxmega64A3 | ATxmega64A1 |
|---|---|---|
| Package | 64-lead TQFP or QFN | 100-lead TQFP, CBGA or VFBGA |
| General-purpose lines | 50 | 78 |
| Serial ports | 7 | 8 |
| SPI channels | 3 | 4 |
| Two-wire channels | 2 | 4 |
| Digital to analog | one dual channel | two dual channel |
| Timers | 7 | 8 |
| Identification | 1E 96 42 | 1E 96 4E |
The identification row is the one to remember. Both parts answer with the same vendor code and the same density code, and only the third field separates them. A reader that keeps two fields will report a 64A3 as a 64A1, and the mistake then propagates into the quote, the plan and the customer’s expectation.
Why the Difference Matters After Delivery
Suppose a recovered image from a 64A3 is dropped into a 64A1 as a temporary substitute while a replacement board is designed. The code will boot, because the array layout, the page size and the vector placement are the same. Then functions will fail in ways that look like software faults: a third serial port that never transmits, a fourth SPI device that reads back zeros, a DAC channel that outputs nothing.
None of those are software faults. The instructions are writing to addresses that exist on the A3 and do not exist on the A1, or to the same addresses with different functions behind them. Because both parts carry the same memory map for flash, the image runs far enough to be convincing.
The reverse direction fails the same way. Code written for a 64A1 that drives four two-wire channels will compile for a 64A3 and then write to registers that are not there.
What a Capture of This Device Should Include
The application array, the 4 KB boot loader, the 2 KB of EEPROM and the fuse and lock state, each as a separate item with its own checksum. The 256-byte page is worth flagging in the plan: this is the density where the page halves, so any routine that assumes 512 bytes, as every larger part in both lines does, will mis-page the array while returning a file that looks complete.
The boot loader is only 4 KB here, 16 pages, which is smaller than the 8 KB used above 64 KB. A customer who wants to modify a field update mechanism will notice.
The user signature row should be captured as well. It is one page of flash, 256 bytes at this density, and it survives a chip erase by design, so a part taken from a scrapped board can still carry a serial number or calibration constants from its previous life.
Packages, Fixtures and the Optical Route
The 64-lead thin quad flat package is a friendlier decapsulation target than the 100-lead parts: a wider lead pitch, thicker mould compound, more room around the die. The QFN variant is the opposite, with an exposed pad that must stay flat and a thinner body. Neither package changes the array, but both change the schedule.
Where the lock fields are programmed, the programming interface is closed and the work moves to the optical route. The semi-invasive method usually comes first because it leaves the metal intact, and the copy protection overview explains what a lock actually blocks, which is less than the phrase suggests.
Reading Versus Owning
A flash device differs from the older one-time-programmable parts in one important respect: it can be erased and rewritten, which makes the fuse state at the time of capture part of the evidence. The memory technology comparison sets out why that distinction changes the plan, and the reading service describes the standard capture and verification steps used here.
Send the top marking, the package and the board function when booking, and state whether a sibling part from the same product is available. Given how closely the 64A3 and 64A1 resemble each other on paper, a paired read is the fastest way to confirm which one is on the bench. The engineering desk will confirm from the marking before scheduling.