The LPC1813JET100 is an NXP LPC18xx part: a Cortex-M3 at 180 MHz with 512 KB program block and 104 KB runtime memory in a TFBGA100. The contact desk handles decapsulation and the checked archive for the LPC1813JET100 TFBGA100.
Peripheral Set
The LPC18xx character of the LPC1813JET100 comes from the HSADC near 80 Msps and the SCT state-configurable timer built in hardware. What makes a LPC1813JET100 more than a generic Cortex-M3 is the HSADC and the SCT, both configured by code in 512 KB program block. The STM32 readout case shows how a cloned board must reconstruct the clock source for the LPC1813JET100.
Flash And Working Memory
The LPC1813JET100 maps 512 KB program block for execution and 104 KB runtime memory for data, with an EMC that can attach off-die SDRAM. Because the LPC1813JET100 includes an external-memory controller, a board may place code or data in off-chip SDRAM through the EMC. A PIC clone example shows how timer configuration lives in a few registers a hex can rebuild.
Reporting And Hand-Off
Delivery is one Intel HEX at the true addresses, a binary per region, and a report listing the CRP state and boot source. Customers get an Intel HEX merging all regions at real addresses, separate binaries, and a short report for the LPC1813JET100 TFBGA100. A related write-up on the LPC1817JBD144 covers the rest of this part family.
Where The Read Protection Lives
The LPC1813JET100 guards its array with a code-read-protection bit in the code flash signature and OTP area, a reversible setting. NXP’s CRP on the LPC1813JET100 is a bit in the code flash signature region that blocks debugger reads but never erases the array. The memory-type comparison explains why flash and option regions are archived separately on the TFBGA100.
Bench Routine
We read 512 KB program block (or the SPIFI device on flashless parts), the OTP and signature area, then a live RAM image, then re-check. The capture order on the LPC1813JET100 is on-die flash or SPIFI image first, then the OTP region, then any live RAM, then a second pass.
A LPC1813JET100 recovered for a warranty claim ships with the evidence package the TFBGA100 board provides.
The 512 KB program block on the LPC1813JET100 is read at the true addresses, not a relocated image a tool might invent.
We note any CAN or USB use on the TFBGA100, because the LPC1813JET100 peripheral setup lives in the flash.
For field units the LPC1813JET100 usually has no source; the recovered image is the only copy that survives.
We store the TFBGA100 board in anti-static foam until the read is done and the files are handed over.
Where decapsulation was needed the bare die of the LPC1813JET100 is photographed before the lid is fully removed.
We separate the 512 KB program block from working memory in the archive, since mixing them hides the lock state.
The LPC1813JET100 is photographed next to a scale so the package size is unambiguous in the archive.
Where the LPC1813JET100 arrived with corroded pins, we clean the TFBGA100 before the first bench attempt.
The report includes the option bytes or signature contents so the LPC1813JET100 lock can be re-applied if required.
We confirm the 100-pin count against the marking so the recovered LPC1813JET100 netlist lines up with the board.
A 100-pin LPC1813JET100 that failed a previous shop usually still yields to a careful second pass.
For a 100-pin LPC1813JET100 the alternate-function pins are decoded from the dump, not guessed from the silk.
Most LPC1813JET100 jobs arrive with no compiler project, only the physical part and a failed recovery attempt.
The Cortex-M3 running at 180 MHz clock source is noted for the LPC1813JET100, because a clone with the wrong PLL will not start.
The Cortex-M3 running at 180 MHz on the LPC1813JET100 runs the recovered code in place, so the cover report notes the boot setup for a spare TFBGA100.
We keep the original oscillator value in the report, since a wrong crystal stops a rebuilt 100-pin board.
The customer gets a plain summary with the LPC1813JET100 files, written for a non-engineer to follow.
A recovered LPC1813JET100 is cross-checked against the order photo so the marking matches the report.
A second confirming read is offered when a customer wants proof no weak cell moved on the LPC1813JET100 TFBGA100.
The customer receives the files with a short note on reflashing the TFBGA100 without tripping the lock again.