Two RX24T variants share a 256 KB array and differ in RAM: one has 16 KB, the other 32 KB. R5F524TBADFP is the 32 KB version, and the difference is not cosmetic. A dual-motor control loop with two current reconstructions and a CAN stack needs the extra sixteen kilobytes, and a firmware image built for 32 KB will not fit the 16 KB device even though both parts carry the same flash size.
Two Chips, One Capacity
This is the trap in the RX24T line. Capacity digit B means 256 KB with 32 KB RAM; capacity digit A means 256 KB with 16 KB RAM. Both are 100-pin LFQFP, both read from FFFC0000h, both have 8 KB of E2 data flash. If a customer sends a hex file without the RAM size, the first diagnostic is the size of the initialised data section and the stack reservation: a build that reserves more than sixteen kilobytes of RAM belongs to the B part.
What The Read Returns
The array from FFFC0000h to FFFFFFFFh, split into 2 KB blocks and verified block by block. The E2 data flash as a separate binary. The option bytes from the OFS window, which on a motor design usually encode watchdog behaviour and low-voltage detection rather than anything exotic.
Nothing is erased. The ID code structure at FFFFFFA0h is read, not modified, and the control code byte is reported so a replacement can be set up to accept the same boot-mode connection policy – or to reject it, if the customer wants the new unit locked.
The FPU Question
RX24T has a single-precision FPU, and motor control code uses it heavily: Park and Clarke transforms, per-unit scaling, observer maths. When a dump is handed to a rebuild team, one of the first questions is always whether the application actually used the FPU or ran soft-float. That is visible in the instruction mix and worth reporting, because a replacement compiled without hardware floating point will meet the same functional spec and miss the loop timing.
Timing, Not Just Code
At 80 MHz with a 2 KB ROM cache, access timing depends on cache behaviour, and a control loop tuned around cached execution can behave differently when the same code runs from a slower path. The register capture, when available, records the clock tree configuration – PLL multipliers, divider settings, and the flash interface clock – which is what a rebuild needs in order to reproduce the timing rather than approximate it. Without it, a replacement can pass a no-load test and still trip on acceleration, because the current loop samples later than the original design ever did.
Deliverables
Intel HEX, E2 binary, option bytes, block map, ID code page, and a note on whether the FPU and the ROM cache were enabled in the captured configuration.
Recording What The FPU Was Doing
Single-precision floating point is fast on RXv2 and slow when emulated, and the difference shows up in loop timing rather than in function. A rebuild that compiles the same algorithm with software floating point will pass every functional test and still miss its current-loop deadline at high speed.
The report therefore states whether the captured configuration had the FPU enabled and whether the interrupt handlers used floating point. That single line prevents a mistake that is otherwise only discovered when a motor is asked to run at rated speed, typically on the customer’s test stand rather than on ours.
Sending A Unit
Note the DC bus voltage and whether the board drives one motor or two. Pack it against foam without removing the heatsink; the thermal path is part of how the unit was qualified.
Start with the services desk or the contact form. The 16 KB RAM version is R5F524TAADFP, and the 384 KB part is R5F524TCADFP.