The PIC18F8680 is the 64 KB member of the PIC18F6585/8585/6680/8680 family documented in DS30491C — the same die as the PIC18F8585 with 16 KB more flash. Everything else matches: 3,328 bytes of SRAM, 1,024 bytes of data EEPROM, a 16-channel 10-bit A/D converter, 69 I/O lines in an 80-pin TQFP, and the two features that define this family: the ECAN module and the external memory bus. These are automotive parts — AEC-Q100 screened — which is why requests for them keep arriving years after newer families have replaced them on the shelf.
Sizes and Boundaries
Flash occupies byte addresses 0x000000 to 0x00FFFF: 4,096 Intel HEX records at 16 bytes. The four code protection blocks quarter the array into 16 KB regions, gated by CP0 through CP3. A locked part reads back constants for the protected blocks while the device ID at 0x3FFFFE and the configuration words at 0x300000 stay readable. Erased cells read 0xFFFF; protected or absent ones read 0x0000, and the ID read is what separates the two meanings.
The Clock Cap That Comes With the Bus
Both 80-pin members of this family carry the external memory interface, and the interface costs frequency: these devices run DC to 40 MHz normally, but drop to DC–25 MHz when the external bus is enabled. That constraint is silicon, not configuration, but it produces a classic recovery puzzle: a board with a 40 MHz crystal, an image whose oscillator configuration assumes the bus is active, and a rebuilt unit that appears to run slow. The configuration words decide whether the bus is in use, which is one more reason they are read and delivered alongside the array rather than treated as an afterthought.
ECAN and What Lives Where
The ECAN module speaks CAN 2.0B with programmable buffers, acceptance filters and masks. The filter map is written by the firmware at start-up, so it is inside the image — but the message traffic the product actually handled is not, and neither are the calibration constants that typically live in the 1,024-byte EEPROM at 0xF00000. For an automotive node, a rebuilt unit with correct code and a wiped EEPROM enumerates on the bus and misreports the data. Read the EEPROM separately, twice, and deliver it as its own region.
Endurance asymmetry is the quiet detail in automotive EEPROM work. This store typically accumulates write cycles at rates the flash never sees — ignition-cycle logs, fault records written on every trip. Cells near the front can read marginally on a first pass long before the part reports any problem, which is why two passes are the floor and a third pass arbitrates rather than an average: averaging a marginal cell with a clean one produces a plausible wrong value, and in a CAN node a plausible wrong value is worse than an obvious failure.
Family Substitution in Practice
Within the quartet the substitution rule is simple: a 6585 or 8585 image (48 KB) runs on the 6680 or 8680 unchanged; the reverse fails for anything placed above 0x00BFFF. The 64-pin members lack the external bus, so an image that touches EMA registers identifies its part as an 80-pin device regardless of what the marking claims. When stock of the original part is gone, moving up one step within the family is usually the cheap fix — after confirming which device the board actually carries by reading the ID, not by reading the top line of the package.
Spotting a Bus-Heavy Image
Firmware built around the external memory interface is recognisable in the dump before any pinout is consulted. Table reads through the bus show up as dense, regularly spaced constant regions addressed above 0x00FFFF — addresses no internal array of this family contains. A file with such regions is telling you the design moved lookup data off-chip, and a delivery that stops at the internal array is half a product: the on-board memory devices have to be read from the board as a separate step. Say which case applies before promising a rebuild, because the difference decides whether the job ends at the die or continues on the PCB.
The 64-pin members of the family — the 6585 and 6680 — carry no external bus and no EMA clock cap; their images never reference addresses above the internal array. That asymmetry is another identification handle when the marking is worn: an image full of above-array addresses belongs to the 80-pin parts, whatever the package in hand says.
Verification
Two independent flash passes compared byte for byte, config words and EEPROM delivered separately, the reset vector resolved, each 16 KB block tail scanned for holes, and the ID reconciled against the marking. Chip extraction analysis covers the review, reading the program memory the two-pass standard, and reading MCU firmware what a verified image means for a rebuild.
Send the ordering suffix and what the node does on the bus. The services page lists deliverables; contact us for a specific device.