Setting the CREN bit of the RCSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation from Microchip PIC16F1783 MCU Code Extraction. Setting the SPEN bit of the RCSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input.
The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits:
- CREN = 1
- SYNC = 0
- SPEN = 1
All other EUSART control bits are assumed to be in their default state. The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero when Extract MCU PIC18F6622 Code.
The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit for the process of Copy Heximal Of Secured MCU PIC18F6720.
If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR.
One final bit time is measured and the level sampled. This is the Stop bit, which is always a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character only after the completion of Extract Program Of Microchip MCU PIC18F6680.
See Section 22.1.2.4 “Receive Framing Error” for more information on framing errors.
Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set when Crack MCU. The top character in the FIFO is transferred out of the FIFO by reading the RCREG register.
