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The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTA register is set the EUSART will shift 9 bits out for each character transmitted.
The TX9D bit of the TXSTA register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the 8 Least Significant bits into the TXREG.
All nine bits of data will be transferred to the TSR shift register immediately after the TXREG is written to to achieve the purpose of Read IC ATMEGA461 Program. A special 9-bit Address mode is available for use with multiple receivers. See Section 12.1.2.7 “Address Detection” for more information on the Address mode.
Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 12.3 “EUSART Baud Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the 8 Least Significant data bits are an address when the receiver is set for address detection only after the completion of Extract IC ATMEGA261P Firmware.
Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set.
If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREG register. This will start the transmission. The Asynchronous mode would typically be used in RS-232 systems..
The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate when Unlock Microcontroller.
When all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory if Crack Locked PIC16F882 MCU.
The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver.
The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register.
